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Några andra slumpade jobb:
- DFT Engineer- Stockholm
- ASIC DFT Engineer- Lund
- IC DFT Engineer- Malmö
- Senior IC DFT Engineer- Malmö
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DFT EngineerJob description The candidate chosen for this position will be working as DFT engineer within a Digital ASIC project for a cutting edge, industry leading 4G modem product. You will be responsible for specification, development, implementation and verification of DFT functionality in a modem subsystem. You will do this together with a team of 5-6 peers. The work includes: Design specification. Design documentation. DFT RTL design. Scan insertion. ATPG generation and verification. BIST implementation and verification. Netlist simulation. IEEE1500 usage. Etc. Required competence Experience in DFT methodology: Scan, BIST, ATPG. Experience in DFT RTL design. Experience of scan insertion using i.e. DFT Compiler. Experience in ATPG using i.e. TetraMax. Experience of netlist simulation using i.e. using Questasim. Excellent verbal and written communication skills. Wanted competence Experience in Design synch version control system. Experience of IEEE1500 implementation. Strong scripting skills. Knowledge of test engineering. Knowledge of production test. A successful candidate is an ASIC DFT Engineer with some experience and good understanding of DFT in advanced ASICs. Both written and spoken English skills are required.
Företag: AURENAV SWEDEN FILIAL AV AURENAV LLC USA
Ort: Stockholm
Publicerad : 09-11
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ASIC DFT Engineer
We are on behalf of one of our customer in Lund looking for an ASIC DFT Engineer. - NOTE: use .doc or docx-format for your application, not pdf! - Short recruitment time on this assignment, apply ASAP! Job description The candidate chosen for this position will be working as DFT engineer within an company Digital ASIC project for a cutting edge, industry leading 4G modem product. You will be responsible for specification, development, implementation and verification of DFT functionality in a modem subsystem. You will do this together with a team of 5-6 peers. The work includes: - Design specification. - Design documentation. - DFT RTL design. - Scan insertion. - ATPG generation and verification. - BIST implementation and verification. - Netlist simulation. - IEEE1500 usage. - Etc. Required competence - Experience in DFT methodology: Scan, BIST, ATPG. - Experience in DFT RTL design. - Experience of scan insertion using i.e. DFT Compiler. - Experience in ATPG using i.e. TetraMax. - Experience of netlist simulation using i.e. using Questasim. - Excellent verbal and written communication skills. Wanted competence - Experience in Design synch version control system. - Experience of IEEE1500 implementation. - Strong scripting skills. - Knowledge of test engineering. - Knowledge of production test. A successful candidate is an ASIC DFT Engineer with some experience and good understanding of DFT in advanced ASICs. Both written and spoken English skills are required. Personal profile should also include a positive attitude, that you enjoy working in a team and you are focused on reaching result on time. As a person you must be thorough and able to work with different people in different sites. Start: October. Duration: 6 months with possibility for further extension. Location: Lund Required languages: Swedish & English Please, apply directly via mail with: - Your updated CV in .doc format - 2 references (people)
Företag: Vasa Consulting AB
Ort: Lund
Publicerad : 09-12
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IC DFT Engineer
Position u-blox is highly specialized in baseband and RF ASIC design. Our designs result in advanced system-on-chip solutions typically including an ARM CPU, peripherals, and dedicated baseband communications processing hardware. u-blox is a fabless company, focusing on key IP development. For DFT positions u-blox aims at a wide span of responsibilities in order to establish a challenging and diversified work environment. As a DFT engineer, you will be responsible for ensuring optimal chip testability at die and package level. Furthermore you will be responsible for defining and integrating proper DFT architecture (including blocks, BISTs, TAP controllers) and also for scan insertion, pattern generation and pattern debugging. In addition you will support quality department with failure mode and RMA analysis. Tasks Writing DFT specification Design/integrate DFT structures as required Responsible for SCAN insertion and pattern generation Verification/validation of developed blocks Ensure readiness for production Writing DFT related SDC constraints Support failure analysis Support test program development Support in defining tester/load boards requirements Digital IC design Requirements Masters Degree in Electrical Engineering or equivalent Minimum 5 year experience in DFT: knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST, LBIST and trade-offs between test quality and test time. Experience in debugging ATPG patterns, Compressed ATPG patterns, MBIST, LBIST and JTAG related issues. Experience with STA constraints development and analysis for DFT modes and SDF simulations Used to work independently and precisely Good communications skills Fluent in English
Företag: u-blox i Malmö AB
Ort: Malmö
Publicerad : 11-23
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Senior IC DFT Engineer
u-blox is highly specialized in baseband and RF ASIC design. Our designs result in advanced system-on-chip solutions typically including an ARM CPU, peripherals, and dedicated baseband communications processing hardware. u-blox is a fabless company, focusing on key IP development. For Sr DFT positions u-blox aims at a wide span of responsibilities in order to establish a challenging and diversified work environment. As a Sr DFT engineer, you will be responsible for ensuring optimal chip testability at die and package level, as well as setting up and run synthesis on top-level. Furthermore you will be responsible for defining and integrating proper DFT architecture (including blocks, BISTs, TAP controllers) and also for scan insertion, pattern generation and pattern debugging. In addition you will support quality department with failure mode and RMA analysis. ⢠Setting up and run Synthesis on top-level ⢠Writing DFT specification ⢠Design/integrate DFT structures as required ⢠Responsible for SCAN insertion and pattern generation ⢠Verification/validation of developed blocks ⢠Ensure readiness for production ⢠Writing DFT related SDC constraints ⢠Support failure analysis ⢠Support test program development ⢠Support in defining tester/load boards requirements ⢠Digital IC design ⢠Masterâs Degree in Electrical Engineering or equivalent ⢠Minimum 5 year experience in Top-level Synthesis ⢠Experience in DFT: knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST, LBIST and trade-offs between test quality and test time. ⢠Experience in debugging ATPG patterns, Compressed ATPG patterns, MBIST, LBIST and JTAG related issues. ⢠Experience with STA constraints development and analysis for DFT modes and SDF simulations ⢠Used to work independently and precisely ⢠Good communications skills ⢠Fluent in English ⢠Valid work permit for Sweden Swiss-based u-blox (SIX:UBXN) is the global leader in wireless and positioning semiconductors for the automotive, industrial and consumer markets. Our solutions enable people, vehicles and machines to locate their exact position and wirelessly communicate via voice, text or video. With a broad portfolio of chips, modules and software solutions, u-blox is uniquely positioned to allow OEMs to develop innovative solutions that enable mobility quickly and cost-effectively. With headquarters in Thalwil, Switzerland, u-blox is globally present with offices in Europe, Asia and the USA.
Företag: u-blox i Malmö AB
Ort: Malmö
Publicerad : 01-11
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